View ISL12022IBZ_7690237.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ? fn6659.2 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. i 2 c bus? is a trademark owned by nxp semiconductors netherlands, b.v. copyright intersil americas inc. 2008, 2009. all rights reserved all other trademarks mentioned are the property of their respective owners. isl12022 real time clock with on chip 5ppm temp compensation low power rtc with battery-backed sram and embedded temp compensation 5 ppm with auto da ylight saving the isl12022 device is a low power real time clock with an embedded temp sensor for oscillator compensation, clock/calendar, power fail, low battery monitor, brownout indicator, single periodic or polled alarms, intelligent battery-backup switching, battery reseal? function and 128 bytes of battery-backed user sram. the oscillator uses an external, low-cost 32.768khz crystal. the real time clock tracks time with separate registers for hours, minutes, and seconds. the device has calendar registers for date, month, ye ar and day of the week. the calendar is accurate through 2 099, with automatic leap year correction. daylight savings time adjustment is done automatically, using parameters entered by the user. power fail and battery monitors offer user-selectable trip levels. a time stamp function records the time and date of switchover from v dd to v bat power, and also from v bat to v dd power. pinout isl12022 (8 ld soic) top view features ? real time clock/calendar - tracks time in hours, minutes and seconds - day of the week, day, month and year ? on-chip oscillator compensa tion over the operating te m p r a n g e - 5ppm over -40c to +85c ? 10-bit digital temperature sensor output - 2c accuracy ? customer programmable day light saving time ? 15 selectable frequency outputs ? 1 alarm - settable to the second, minute, hour, day of the week, day, or month - single event or pulse interrupt mode ? battery reseal? function to extend battery shelf life ? automatic backup to batt ery or super capacitor - operation to v bat = 1.8v - 1.0a battery supply current ? battery status monitor - 2 user programmable levels - seven selectable voltages for each level ? power status brownout monitor - six selectable trip levels, from 2.295v to 4.675v ? oscillator failure detection ? time stamp for first v dd to v bat , and last v bat to v dd ? 128 bytes batter y-backed user sram ?i 2 c bus? - 400khz clock frequency ? 8 ld soic package ? pb-free (rohs compliant) applications ? utility meters ? pos equipment ? medical devices ? security systems ? vending machines ? white goods ? printers and copiers v dd irq /f out scl sda x1 x2 v bat 1 2 3 4 8 7 6 5 gnd data sheet june 23, 2009
2 fn6659.2 june 23, 2009 block diagram ordering information part number (note) part marking v dd range (v) temp range (c) package (pb-free) pkg. dwg. # ISL12022IBZ* 12022 ibz 2.7 to 5.5 -40 to +85 8 ld soic m8.15 *add ?-t? suffix for tape and reel. please refe r to tb347 for details on reel specifications. note: these intersil pb-free plastic packa ged products employ special pb-free material sets, molding compounds/die attach materi als, and 100% matte tin plate plus anneal (e3 termination fi nish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements o f ipc/jedec j std-020. i 2 c interface control logic alarm frequency out rtc divider sda buffer crystal oscillator por switch scl buffer sda scl x1 x2 v dd v bat irq /f out internal supply v trip seconds minutes hours day of week date month year user sram control registers gnd registers temperature sensor frequency control pin descriptions pin number symbol description 1x1 crystal input . the x1 pin is the input of an inverting ampl ifier and is intended to be connected to one pin of an external 32.768khz quartz crystal. x1 can also be driven directly from a 32.768khz source. 2x2 crystal output . the x2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768khz quartz crystal. x2 should be le ft open when x1 is driven from external source. 3v bat backup supply. this input provides a backup supply voltage to the device. v bat supplies power to the device in the event that the v dd supply fails. this pin shoul d be tied to ground if not used. 4gnd ground . 5sda serial data . sda is a bi-directional pin used to transfer serial data into and out of the device. it has an open drain output and may be wire or?ed with other open drain or open collector outputs. 6scl serial clock . the scl input is used to clock all se rial data into and out of the device. 7irq /f out interrupt output/frequency output. multi-functional pin that can be used as interrupt or frequency output pin. the function is set via the configurati on register. it is an open-drain output. 8v dd power supply . isl12022
3 fn6659.2 june 23, 2009 absolute maximum rati ngs thermal information voltage on v dd , v bat and irq /f out pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v voltage on scl and sda pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd +0.3v voltage on x1 and x2 pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.5v esd rating human body model (per mil-std-883 method 3014) . . . . .>3kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>300v thermal resistance (typical, note 1) ja (c/w) 8 ld soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. dc operating characteristics - rtc test conditions: v dd = +2.7 to +5.5v, t a = -40c to +85c, unless otherwise stated. symbol parameter conditions min (note 9) typ (note 5) max (note 9) units notes v dd main power supply (note 11) 2.7 5.5 v v bat battery supply voltage (note 11) 1.8 5.5 v 2 i dd1 supply current. (i 2 c not active, temperature conversion not active, f out not active) v dd = 5v 4.1 7 a 3, 4 v dd = 3v 3.5 6 a 3, 4 i dd2 supply current. (i 2 c active, temperature conversion not active, f out not active) v dd = 5v 200 500 a 3, 4 i dd3 supply current. (i 2 c not active, temperature conversion active, f out not active) v dd = 5v 120 400 a 3, 4 i bat battery supply current v dd = 0v, v bat = 3v, t a = +25c 1.0 1.6 a 3 v dd = 0v, v bat = 3v 1.0 5.0 a 3 i batlkg battery input leakage v dd = 5.5v, v bat = 1.8v 100 na i li input leakage current on scl v il = 0v, v ih = 5.5v -1.0 0.1 1.0 a i lo i/o leakage current on sda v il = 0v, v ih = 5.5v -1.0 0.1 1.0 a v batm battery level monitor threshold -100 +100 mv v pbm brownout level monitor threshold -100 +100 mv v trip v bat mode threshold (note 11) 2.0 2.2 2.4 v v triphys v trip hysteresis 30 mv 7 v bathys v bat hysteresis 50 mv 7 fout t oscillator stability vs temperature v dd = 3.3v -5 +5 ppm 10 fout v oscillator stability vs voltage 2.7v v dd 5.5v -3 +3 ppm 10 at lsb at sensitivity per lsb beta (4:0) = 10000 0.5 1 2 ppm 10 temp temperature sensor accuracy v dd = v bat = 3.3v 2 c 7 irq /f out (open drain output) v ol output low voltage v dd = 5.5v, i ol = 3ma 0.4 v v dd = 2.7v, i ol = 1ma 0.4 v isl12022
4 fn6659.2 june 23, 2009 power-down timing test conditions: v dd = +2.7 to +5.5v, t a = -40c to +85c, unless otherwise stated. symbol parameter conditions min (note 9) typ (note 5) max (note 9) units notes v dd sr- v dd negative slew rate 10 v/ms 6 i 2 c interface specifications test conditions: v dd = +2.7 to +5.5v, t a = -40c to +85c, unless otherwise specified. symbol parameter test conditions min (note 9) typ (note 5) max (note 9) units notes v il sda and scl input buffer low voltage -0.3 0.3 x v dd v v ih sda and scl input buffer high voltage 0.7 x v dd v dd + 0.3 v hysteresis sda and scl input buffer hysteresis 0.05 x v dd v7, 8 v ol sda output buffer low voltage, sinking 3ma v dd = 5v, i ol = 3ma 0 0.02 0.4 v c pin sda and scl pin capacitance t a = +25c, f = 1mhz, v dd = 5v, v in =0v, v out = 0v 10 pf 7, 8 f scl scl frequency 400 khz t in pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed. 50 ns t aa scl falling edge to sda output data valid scl falling edge crossing 30% of v dd , until sda exits the 30% to 70% of v dd window. 900 ns t buf time the bus must be free before the start of a new transmission sda crossing 70% of v dd during a stop condition, to sda crossing 70% of v dd during the following start condition. 1300 ns t low clock low time measured at the 30% of v dd crossing. 1300 ns t high clock high time measured at the 70% of v dd crossing. 600 ns t su:sta start condition setup time scl rising edge to sda falling edge. both crossing 70% of v dd . 600 ns t hd:sta start condition hold time from sda falling edge crossing 30% of v dd to scl falling edge crossing 70% of v dd . 600 ns t su:dat input data setup time from sda exiting the 30% to 70% of v dd window, to scl rising edge crossing 30% of v dd. 100 ns t hd:dat input data hold time from scl falling edge crossing 30% of v dd to sda entering the 30% to 70% of v dd window. 0 900 ns t su:sto stop condition setup time from scl rising edge crossing 70% of v dd , to sda rising edge crossing 30% of v dd . 600 ns isl12022
5 fn6659.2 june 23, 2009 t hd:sto stop condition hold time from sda rising edge to scl falling edge. both crossing 70% of v dd . 600 ns t dh output data hold time from scl falling edge crossing 30% of v dd , until sda enters the 30% to 70% of v dd window. 0ns t r sda and scl rise time from 30% to 70% of v dd. 20 + 0.1 x cb 300 ns 8 t f sda and scl fall time from 70% to 30% of v dd. 20 + 0.1 x cb 300 ns 8 cb capacitive loading of sda or scl total on-chip and off-chip 10 400 pf 8 r pu sda and scl bus pull-up resistor off-chip maximum is determined by t r and t f . for cb = 400pf, max is about 2k ~2.5k . for cb = 40pf, max is about 15k ~20k 1k 8 notes: 2. temperature conversion is inactive below v bat = 2.7v. device operation is not guaranteed at vbat<1.8v. 3. irq/ f out inactive. 4. v dd > v bat +v bathys 5. specified at +25c. 6. in order to ensure proper timekeeping, the v dd sr- specification must be followed. 7. limits should be considered ty pical and are not production tested. 8. these are i 2 c specific parameters and are not tested, however, they ar e used to set conditions for testing devices to validate specification. 9. parameters with min and/or max limits are 100% tested at + 25c, unless otherwise specified. temperature limits established by characterization and are not production tested. 10. specifications are typical and require using a re commended crystal (see ?application section? on page 25). 11. minimum v dd and/or v bat of 1v to sustain the sram. the value is based on characterization and it is not tested. i 2 c interface specifications test conditions: v dd = +2.7 to +5.5v, t a = -40c to +85c, unless otherwise specified. (continued) symbol parameter test conditions min (note 9) typ (note 5) max (note 9) units notes isl12022
6 fn6659.2 june 23, 2009 sda vs scl timing symbol table t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda (input timing) sda (output timing) t f t low t buf t aa t r waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance figure 1. standard output load for testing the device with v dd = 5.0v sda and irq /f out 1533 100pf 5.0v for v ol = 0.4v and i ol = 3ma equivalent ac output load circuit for v dd = 5v isl12022
7 fn6659.2 june 23, 2009 typical performance curves temperature is +25c unless otherwise specified. figure 2. i bat vs v bat figure 3. i bat vs temperature figure 4. i dd1 vs temperature figure 5. i dd1 vs v dd figure 6. f out vs i dd figure 7. i dd vs temperature, 3 different f out 800 850 900 950 1000 1050 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v bat voltage (v) v bat current (na) 600 800 1000 1200 1400 1600 -40-20 0 20406080 temperature (c) i bat (na) v bat = 1.8v v bat = 3.0v v bat = 5.5v 2 3 4 5 6 -40-20 0 20406080 temperature (c) i dd1 (a) v bat = 2.7v v dd = 3.3v v bat = 5.5v 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 2.73.23.74.24.75.2 v dd (v) i dd1 (a) 2 3 4 5 6 0.01 0.1 1 10 100 1k 10k 100k frequency output (hz) i dd (a) v dd = 2.7v v dd = 3.3v v dd = 5.5v 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40-20 0 20406080 temperature (c) supply current (a) f out = 32khz f out = 1hz and 64hz isl12022
8 fn6659.2 june 23, 2009 general description the isl12022 device is a low power real time clock (rtcs) with embedded temperature sensors. it contains crystal frequency compensation circuitry over the operating temperature range, clock/calendar, power fail and low battery monitors, brownout indicator, 1 periodic or polled alarm, intelligent battery-backup switching and 128 bytes of battery-backed user sram. the oscillator uses an external, low cost 32.768khz crystal. the real time clock tracks time with separate registers for hours, minutes and seconds. the device has calendar registers for date, month, ye ar and day of the week. the calendar is accurate through 2 099, with automatic leap year correction. in addition, the isl12022 can be programmed for automatic daylight savings time (dst) adjustment by entering local dst information. the isl12022?s alarm can be set to any clock/calendar value for a match, for example, every minute, every tuesday or at 5:23 am on march 21. the alarm status is available by checking the status register, or the device can be configured to provide a hardware interrupt via the irq /f out pin. there is a repeat mode for the alarm allowing a periodic interrupt every minute, every hour, every day, etc. the device also offers a backup power input pin. this v bat pin allows the device to be backed up by battery or super capacitor with automati c switchover from v dd to v bat . the isl12022 device is specified for v dd = 2.7v to 5.5v and the clock/calendar portion of the device remains fully operational in battery-backup mode down to 1.8v (standby mode). the v bat level is monitored and reported against preselected levels. the first report is registered when the v bat level falls below 85% of nominal level, the second level is set for 75%. battery levels are stored in pwr_vbat registers. the isl12022 offers a ?brownout? alarm once the v dd falls below a pre-selected trip level. this al lows system micro to save vital information to me mory before complete power loss. there are six v dd levels that could be selected for initiation of the brownout alarm. pin descriptions x1, x2 the x1 and x2 pins are the input and output, respectively, of an inverting amplifier. an external 32.768khz quartz crystal is used with the device to supply a timebase for the real time clock. internal compensation circuitry with internal temperature sensor provides frequency corrections for selected popular crystals to 5ppm over the operating temperature range from -40c t o +85c. (see ?application section? on page 25 for recommended crystal). the isl12022 allows the user to input via i 2 c serial bus the temperature variation profile of an individual crystal. the oscillator compensation network can also be used to calibrate the initial crystal timing accuracy to less than 1ppm error at room temperature. the device can also be driven directly from a 32.768khz source at pin x1. v bat this input provides a backup supply voltage to the device. v bat supplies power to the device in the event that the v dd supply fails. device power wi ll automatically switch to the v bat input when v dd drops below the switchover trip level (v trip ) . this pin can be connected to a battery, a super capacitor or tied to ground if not used. irq /f out (interrupt output/frequency output) this dual function pin can be used as an interrupt or frequency output pin. the irq /f out mode is selected via the frequency out control bits of the control/status register. it is an open drain output. figure 8. i dd with tse = 1 vs temperature figure 9. i bat with tse = 1, btse = 1 vs temperature typical performance curves temperature is +25c unless otherwise specified. (continued) 40 50 60 70 80 90 100 110 -40-20 0 20406080 temperature (c) i dd (a) v bat = 2.7v v dd = 3.3v v dd = 5.5v 20 30 40 50 60 70 80 90 100 110 -40-20 0 20406080 temperature (c) i bat (a) v bat = 1.8v v bat = 3.0v v bat = 5.5v figure 10. recommended crystal connection x1 x2 isl12022
9 fn6659.2 june 23, 2009 ? interrupt mode. the pin provides an interrupt signal output. this signal notifies a host processor that an alarm has occurred and requests action. it is an active low output. ? frequency output mode. the pin outputs a clock signal, which is related to the crystal frequency. the frequency is user selectable and enabled via the i 2 c bus. serial clock (scl) the scl input is used to clock all serial data into and out of the device. the input buffer on this pin is always active (not gated). it is disabled when the backup power supply on the v bat pin is activated to minimize power consumption. serial data (sda) sda is a bi-directional pin used to transfer data into and out of the device. it has an open drain output and may be ored with other open drain or open co llector outputs. the input buffer is always active (not gated) in normal mode. an open drain output requires the use of a pull-up resistor. the output circuitry controls the fa ll time of the output signal with the use of a slope contro lled pull-down. the circuit is designed for 400khz i 2 c interface speeds. it is disabled when the backup power supply on the v bat pin is activated. v dd , gnd chip power supply and ground pins. the device will operate with a power supply from v dd = 2.7v to 5.5vdc. a 0.1f capacitor is recommended on the v dd pin to ground. functional description power control operation the power control circuit accepts a v dd and a v bat input. many types of batteries can be used with intersil rtc products. for example, 3.0v or 3.6v lithium batteries are appropriate, and battery sizes are available that can power the isl12022 for up to 10 years. another option is to use a super capacitor for applications where v dd is interrupted for up to a month. see the ?application section? on page 25 for more information. normal mode (v dd ) to battery-backup mode (v bat ) to transition from the v dd to v bat mode, both of the following conditions must be met: condition 1: v dd < v bat - v bathys where v bathys 50mv condition 2: v dd < v trip where v trip 2.2v battery-backup mode (v bat ) to normal mode (v dd ) the isl12022 device will switch from the v bat to v dd mode when one of the following conditions occurs: condition 1: v dd > v bat + v bathys where v bathys 50mv condition 2: v dd > v trip + v triphys where v triphys 30mv these power control situations are illustrated in figures 11 and 12. the i 2 c bus is deactivated in battery-backup mode to reduce power consumption. aside from this, all rtc functions are operational during battery-backup mode. except for scl and sda, all the inputs and outputs of the isl12022 are active during battery-backup mode unless disabled via the control register. the device time stamps the switchover from v dd to v bat and v bat to v dd , and the time is stored in t sv2b and t sb2v registers respectively. if multiple v dd power-down sequences occur before status is read, the earliest v dd to v bat power-down time is stored and the most recent v bat to v dd time is stored. temperature conversion and compensation can be enabled in battery-backup mode. bi t btse in the beta register controls this operation, as described in ?beta register (beta)? on page 17. v bat - v bathys v bat v bat + v bathys battery-backup mode v dd v trip 2.2v 1.8v figure 11. battery switchover when v bat < v trip figure 12. battery switchover when v bat > v trip v trip v bat v trip + v triphys battery-backup mode v dd v trip 3.0v 2.2v isl12022
10 fn6659.2 june 23, 2009 power failure detection the isl12022 provides a real time clock failure bit (rtcf) to detect total power failure. it allows users to determine if the device has powered up after having lost all power to the device (both v dd and v bat ). brownout detection the isl12022 monitors the v dd level continuously and provides warning if the v dd level drops below prescribed levels. there are six (6) levels that can be selected for the trip level. these values are 85% below popular v dd levels. the lvdd bit in the status register will be set to ?1? when brownout is detected. note that the i 2 c serial bus remains active unless the battery v trip levels are reached. battery level monitor the isl12022 has a built in warning feature once the back-up battery level drops first to 85% and then to 75% of the battery?s nominal v bat level. when the battery voltage drops to between 85% and 75%, the lbat85 bit is set in the status register. when the level drops below 75%, both lbat85 and lbat75 bits are set in the status register. the battery level monitor is not functional in battery backup mode. in order to read the monitor bits after powering up v dd , instigate a battery level measurement by setting the tse bit to "1" (beta register), and then read the bits. there is a battery time stamp function available. once the v dd is low enough to enable switchover to the battery, the rtc time/date are written into the tsv2b register. this information can be read from the tsv2b registers to discover the point in time of the v dd power-down. if there are multiple power-down cycl es before reading these registers, the first values stored in these registers will be retained. these registers will hold the original power-down value until they are cleared by setting clrts = 1 to clear the registers. the normal power switching of the isl12022 is designed to switch into battery-backup mode only if the v dd power is lost. this will ensure that the device can accept a wide range of backup voltages from many types of sources while reliably switching into backup mode. note that the isl12022 is not guaranteed to operate with v bat < 1.8v. if the battery voltage is expected to drop lower than this minimum, correct operation of the device, especially after a v dd power-down cycle, is not guaranteed. the minimum v bat to insure sram is stable is 1.0v. below that, the sram may be corrupted when v dd power resumes. real time clock operation the real time clock (rtc) uses an external 32.768khz quartz crystal to maintain an accurate internal representation of second, minute, hour, day of week, date, month, and year. the rtc also has leap-year correction. the clock also corrects for months having fewer than 31 days and has a bit that controls 24-hour or am/pm format. when the isl12022 powers up after the loss of both v dd and v bat , the clock will not begin incrementing until at leas t one byte is written to the clock register. single event and interrupt the alarm mode is enabled via the msb bit. choosing single event or interrupt alarm mode is selected via the im bit. note that when the frequency output function is enabled, the alarm function is disabled. the standard alarm allows for alarms of time, date, day of the week, month, and year. when a time alarm occurs in single event mode, the irq /f out pin will be pulled low and the alarm status bit (alm) will be set to ?1?. the pulsed interrupt mode allows for repetitive or recurring alarm functionality. hence, once the alarm is set, the device will continue to alarm for each occurring match of the alarm and present time. thus, it will alarm as often as every minute (if only the nth second is set) or as infrequently as once a year (if at least the nth month is set). during pulsed interrupt mode, the irq /f out pin will be pulled low for 250ms and the alarm status bit (alm) will be set to ?1?. the alm bit can be reset by the user or cleared automatically using the auto reset mode (see arst bit). the alarm function can be enabled/disabled during battery-backup mode using the fobatb bit. for more information on the alarm, please see ?alarm registers (10h to 15h)? on page 19. frequency output mode the isl12022 has the option to provide a clock output signal using the irq /f out open drain output pin. the frequency output mode is set by using the fo bits to select 15 possible output frequency values from 1/32hz to 32khz. the frequency output can be enabled/disabled during battery-backup mode using the fobatb bit. general purpose user sram the isl12022 provides 128 bytes of user sram. the sram will continue to operate in battery-backup mode. however, it should be noted that the i 2 c bus is disabled in battery-backup mode. i 2 c serial interface the isl12022 has an i 2 c serial bus interface that provides access to the control and status registers and the user sram. the i 2 c serial interface is compatible with other industry i 2 c serial bus protocols using a bi-directional data signal (sda) and a clock signal (scl). oscillator compensation the isl12022 provides both initial timing correction and temperature correction due to variation of the crystal oscillator. analog and digital trimming control is provided for initial adjustment, and a temp erature compensation function is provided to automatically correct for temperature drift of isl12022
11 fn6659.2 june 23, 2009 the crystal. initial values are preset and recalled on initial power-up for the initial at and dt settings (iatr, idtr), temperature coefficient (alp ha), crystal capacitance (beta), and the crystal turn-over temperature (xto). these initial values are typical of units available on the market, although the user may program s pecific values after testing for best accuracy. the function can be enabled/disabled at any time and can be used in battery mode as well. register descriptions the battery-backed registers are accessible following a slave byte of ?1101111x? and reads or writes to addresses [00h:2fh]. the defined addresse s and default values are described in the table 1. the battery backed general purpose sram has a different slave address (1010111x), so it is not possible to read/writ e that section of memory while accessing the registers. register access the contents of the register s can be modified by performing a byte or a page write operation directly to any register address. the registers are divided into 8 sections. they are: 1. real time clock (7 bytes): address 00h to 06h. 2. control and status (9 bytes): address 07h to 0fh. 3. alarm (6 bytes): address 10h to 15h. 4. time stamp for battery status (5 bytes): address 16h to 1ah. 5. time stamp for v dd status (5 bytes): address 1bh to 1fh. 6. daylight savings time (8 bytes): 20h to 27h. 7. temp (2 bytes): 28h to 29h 8. crystal net ppm correction, nppm (2 bytes): 2ah, 2bh 9. crystal turnover temperature, xt0 (1 byte): 2ch 10. crystal alpha at high temperature, alpha_h (1 byte): 2dh 11. scratch pad (2 bytes): address 2eh and 2fh write capability is allowable into the rtc registers (00h to 06h) only when the wrtc bit (bit 6 of address 08h) is set to ?1?. a multi-byte read or writ e operation should be limited to one section per operation for best rtc time keeping performance. a register can be read by performing a random read at any address at any time. this returns the contents of that register location. additional registers are read by performing a sequential read. for the rtc a nd alarm registers, the read instruction latches all clock r egisters into a buffer, so an update of the clock does not change the time being read. at the end of a read, the master supplies a stop condition to end the operation and free the bus. after a read, the address remains at the previous addre ss +1 so the user can execute a current address read and continue reading the next register. when the previous address is 2fh, the next address will wrap around to 00h. it is not necessary to set the wrtc bit prior to writing into the control and status, alarm, and user sram registers. table 1. register memory map addr. section reg name bit range default 76543210 00h rtc sc 0 sc22 sc21 sc20 sc13 sc12 sc11 sc10 0 to 59 00h 01h mn 0 mn22 mn21 mn20 mn13 mn12 mn11 mn10 0 to 59 00h 02h hr mil 0 hr21 hr20 hr13 hr12 hr11 hr10 0 to 23 00h 03h dt 0 0 dt21 dt20 dt13 dt12 dt11 dt10 1 to 31 01h 04h mo 0 0 0 mo20 mo13 mo12 mo11 mo10 1 to 12 01h 05h yr yr23 yr22 yr21 yr20 yr13 yr12 yr11 yr10 0 to 99 00h 06h dw00000dw2dw1dw00 to 600h 07h csr sr busy oscf dstadj alm lvdd lbat85 lbat75 rtcf n/a 01h 08h int arst wrtc im fobatb fo3 fo2 fo1 fo0 n/a 01h 09h pwr_vdd clrts d d d d v dd trip2 v dd trip1 v dd trip0 n/a 00h 0ah pwr_vbat resealb vb85tp2 vb85tp1 vb85tp0 vb75tp2 vb75tp1 vb75tp0 n/a 00h 0bh itro idtr01 idtr00 iatr05 iatr04 iatr03 iatr02 iatr01 iatr00 n/a 20h 0ch alpha d alpha6 alpha5 alpha4 alpha3 alpha2 alpha1 alpha0 n/a 46h 0dh beta tse btse btsr beta4 beta3 beta2 beta1 beta0 n/a 00h 0eh fatr 0 0 ffatr5 fatr4 fatr3 fatr2 fatr1 fatr0 n/a 00h 0fh fdtr 0 0 0 fdtr4 fdtr3 fdtr2 fdtr1 fdtr0 n/a 00h isl12022
12 fn6659.2 june 23, 2009 10h alarm sca0 esca0 sca022 sca021 sca020 sca013 sca012 sca011 sca010 00 to 59 00h 11h mna0 emna0 mna022 mna021 mna020 mna013 mna012 mna011 mna010 00 to 59 00h 12h hra0 ehra0 d hra021 hra020 hra013 hra012 hra011 hra010 0 to 23 00h 13h dta0 edta0 d dta021 dta020 dta013 dta012 dta011 dta010 01 to 31 00h 14h moa0 emoa00 d d moa020 moa013 moa012 moa011 moa010 01 to 12 00h 15h dwa0 edwa0 d d d d dwa02 dwa01 dwa00 0 to 6 00h 16h tsv2b vsc 0 vsc22 vsc21 vsc20 vsc13 vsc12 vsc11 vsc10 0 to 59 00h 17h vmn 0 vmn22 vmn21 vmn20 vmn13 vmn12 vmn11 vmn10 0 to 59 00h 18h vhr vmil 0 vhr21 vhr20 vhr13 vhr12 vhr11 vhr10 0 to 23 00h 19h vdt 0 0 vdt21 vdt20 vdt13 vdt12 vdt11 vdt10 1 to 31 00h 1ah vmo 0 0 0 vmo20 vmo13 vmo12 vmo11 vmo10 1 to 12 00h 1bh tsb2v bsc 0 bsc22 bsc21 bsc20 bsc13 bsc12 bsc11 bsc10 0 to 59 00h 1ch bmn 0 bmn22 bmn21 bmn20 bmn13 bmn12 bmn11 bmn10 0 to 59 00h 1dh bhr bmil 0 bhr21 bhr20 bhr13 bhr12 bhr11 bhr10 0 to 23 00h 1eh bdt 0 0 bdt21 bdt20 bdt13 bdt12 bdt11 bdt10 1 to 31 00h 1fh bmo 0 0 0 bmo20 bmo13 bmo12 bmo11 bmo10 1 to 12 00h 20h dstcr dstmofd dste d d dstmofd20 dstmofd13 dstmofd12 dstmofd11 dstmofd10 1 to 12 00h 21h dstdwfd d dstdwfde dstwkfd12 dstwkfd11 dstwkfd10 dstdwfd12 dstdwfd11 dstdwfd10 0 to 6 00h 22h dstdtfd d d dstdtfd21 dstdtfd20 dstdtfd13 dstdtfd12 dstdtfd11 dstdtfd10 1 to 31 00h 23h dsthrfd d d dsthrfd21 dsthrfd20 dsthrfd13 dsthrfd12 dsthrfd11 dsthrfd10 0 to 23 00h 24h dstmorv d d d xdstmorv2 0 dstmorv13 dstmor12v dstmorv11 dstmorv10 01 to 12 00h 25h dstdwrv d dstdwrve dstwkrv12 dstwkrv11 dstwkrv 10 dstdwrv12 dstdwrv11 dstdwrv10 0 to 6 00h 26h dstdtrv d d dstdtrv21 dstdtrv20 dstdtrv13 dstdtrv12 dstdtrv11 dstdtrv10 01 to 31 00h 27h dsthrrv d d dsthrrv21 dsthrrv20 dsthrrv13 dsthrrv12 dsthrrv11 dsthrrv10 0 to 23 00h 28h temp tk0l tk07 tk06 tk05 tk04 tk03 tk02 tk01 tk00 00 to ff 00h 29h tk0m000000tk09tk0800 to 0300h 2ah nppm nppml nppm7 nppm6 nppm5 nppm4 nppm3 nppm2 nppm1 nppm0 00 to ff 00h 2bh nppmh00000nppm10nppm9nppm800 to 0700h 2ch xt0 xt0 d d d xt4 xt3 xt2 xt1 xt0 00 to ff 00h 2dh alphah alphah d alp_h6 alp_h5 alp_h4 alp_h3 alp_h2 alp_h1 alp_h0 00 to 7f 46h 2eh gpm gpm1 gpm17 gpm16 gpm15 gpm14 gpm13 gpm12 gpm11 gpm10 00 to ff 00h 2fh gpm2 gpm27 gpm26 gpm25 gpm24 gpm23 gpm22 gpm21 gpm20 00 to ff 00h table 1. register memory map (continued) addr. section reg name bit range default 76543210 isl12022
13 fn6659.2 june 23, 2009 real time clock registers addresses [00h to 06h] rtc registers (sc, mn, hr, dt, mo, yr, dw) these registers depict bcd repr esentations of the time. as such, sc (seconds) and mn (minutes) range from 0 to 59, hr (hour) can either be a 12-hour or 24-hour mode, dt (date) is 1 to 31, mo (month) is 1 to 12, yr (year) is 0 to 99, and dw (day of the week) is 0 to 6. the dw register provides a day of the week status and uses three bits dw2 to dw0 to represent the seven days of the week. the counter advances in the cycle 0-1-2-3-4-5-6-0-1- 2-? the assignment of a numeri cal value to a specific day of the week is arbitrary a nd may be decided by the system software designer. the default value is defined as ?0?. 24 hour time if the mil bit of the hr register is ?1?, the rtc uses a 24-hour format. if the mil bit is ?0?, the rtc uses a 12-hour format and hr21 bit functions as an am/pm indicator with a ?1? representing pm. the clock defaults to 12-hour format time with hr21 = ?0?. leap years leap years add the day february 29 and are defined as those years that are divisible by 4. ye ars divisible by 100 are not leap years, unless they are also divisible by 400. this means that the year 2000 is a leap year and the year 2100 is not. the isl12022 does not correct for the leap year in the year 2100. control and status registers (csr) addresses [07h to 0fh] the control and status regist ers consist of the status register, interrupt and alarm register, analog trimming and digital trimming registers. status register (sr) the status register is located in the memory map at address 07h. this is a volatile register that provides either control or status of rtc failure (rtcf), battery level monitor (lbat85, lbat75), alarm trigger, daylight savings time, crystal oscillator enable and temperature conversion in progress bit. busy bit (busy) busy bit indicates temperature sensing is in progress. in this mode, alpha, beta and itro registers are disabled and cannot be accessed. oscillator fail bit (oscf) oscillator fail bit indicates that the oscillator has stopped. daylight savings time change bit (dstadj) dstadj is the daylight savings time adjusted bit. it indicates the daylight saving time forward adjustment has happened. if a dst forward event happens, dstadj will be set to ?1?. the dstadj bit will stay high after the dstfd event happens, and will be reset to ?0? when the dst reverse event happens. dstadj can be set to ?1? for instances where the rtc device is initialized during the dst forward period. the dste bit must be enabled when the rtc time is more than one hour before the dst forward or dst reverse event time setting, or the dst ev ent correction will not happen. dstadj is reset to ?0? upon power-up. it will reset to ?0? when the dste bit in register 15h is set to ?0? (dst disabled), but no time adjustment will happen. alarm bit (alm) this bit announces if the alarm matches the real time clock. if there is a match, the respective bit is set to ?1?. this bit can be manually reset to ?0? by the us er or automatically reset by enabling the auto-reset bit (see arst bit). a write to this bit in the sr can only set it to ?0?, not ?1?. an alarm bit that is set by an alarm occurring during an sr read operation will remain set after the read operation is complete. low v dd indicator bit (lvdd) this bit indicates when v dd has dropped below the pre-selected trip level (brownout mode). the trip points for the brownout levels are selected by three bits: vdd trip2, vdd trip1 and vdd trip0 in pwr_ vdd registers. the lvdd detection is only enabled in vdd mode and the detection happens in real time. the lvdd bit is set whenever the v dd has dropped below the pre-selected trip level, and self clears whenever the v dd is above the pre- selected trip level. low battery indicator 85% bit (lbat85) in normal mode (v dd ), this bit indicates when the battery level has dropped below the pre-selected trip levels. the trip points are selected by three bits: vb85tp2, vb85tp1 and vb85tp0 in the pwr_vbat registers. the lbat85 detection happens automatical ly once every minute when seconds register reaches 59. the detection can also be manually triggered by setting the tse bit in beta register to ?1?. the lbat85 bit is set when the v bat has dropped below the pre-selected trip level, and will self clear when the v bat is above the pre-selected trip level at the next detection cycle either by manual or automatic trigger. in battery mode (v bat ), this bit indica tes the device has entered into battery mode by polling once every 10 minutes. the lbat85 detection happens aut omatically once when the minute register reaches x9h or x0h minutes. table 2. status register (sr) addr 7 6 5 4 3 2 1 0 07h busy oscf dstdj alm lvdd lbat85 lbat75 rtcf isl12022
14 fn6659.2 june 23, 2009 example - when the lbat85 is set to ?1? in battery mode: the minute the register changes to 19h when the device is in battery mode, the lbat85 is se t to ?1? the next time the device switches back to normal mode. example - when the lbat85 remains at ?0? in battery mode: if the device enters into battery mode after the minute register reaches 20h and switches back to normal mode before the minute regist er reaches 29h, then the lbat85 bit will remain at ?0? the next time the device switches back to normal mode. low battery indicato r 75% bit (lbat75) in normal mode (v dd ), this bit indicates when the battery level has dropped below the pre-selected trip levels. the trip points are selected by three bits: vb75tp2, vb75tp1 and vb75tp0 in the pwr_vbat registers. the lbat75 detection happens automatical ly once every minute when seconds register reaches 59. the detection can also be manually triggered by setting the tse bit in beta register to ?1?. the lbat75 bit is set when the v bat has dropped below the pre-selected trip level, and will self clear when the v bat is above the pre-selected trip level at the next detection cycle either by manual or automatic trigger. in battery mode (v bat ), this bit indicates the device has entered into battery mode by polling once every 10 minutes. the lbat85 detection happens automatically once when the minute register reaches x9h or x0h minutes. example - when the lbat75 is set to ?1? in battery mode: the minute register changes to 30h when the device is in battery mode, the lbat75 is se t to ?1? the next time the device switches back to normal mode. example - when the lbat75 remains at ?0? in battery mode: if the device enters into battery mode after the minute register reaches 49h and switches back to normal mode before minute register reaches 50h, then the lbat75 bit will remain at ?0? the next time the device switches back to normal mode. real time clock fail bit (rtcf) this bit is set to a ?1? after a total power failure. this is a read only bit that is set by hardware (isl12022 internally) when the device powers up after having lost all power (defined as v dd = 0v and v bat = 0v). the bit is set regardless of whether v dd or v bat is applied first. the loss of only one of the supplies does not set the rtcf bit to ?1?. the first valid write to the rtc section after a complete power failure resets the rtcf bit to ?0? (w riting one byte is sufficient). interrupt control register (int) automatic reset bit (arst) this bit enables/disables the automatic reset of the alm, lvdd, lbat85, and lbat75 status bits only. when arst bit is set to ?1?, these status bits are reset to ?0? after a valid read of the respective status register (with a valid stop condition). when the arst is cleared to ?0?, the user must manually reset the alm, lvdd, lbat85, and lbat75 bits. write rtc enable bit (wrtc) the wrtc bit enables or disables write capability into the rtc timing registers. the factory default setting of this bit is ?0?. upon initialization or power-up, the wrtc must be set to ?1? to enable the rtc. upon the completion of a valid write (stop), the rtc starts counting. the rtc internal 1hz signal is synchronized to the stop condition during a valid write cycle. interrupt/alarm mode bit (im) this bit enables/disables the interrupt mode of the alarm function. when the im bit is set to ?1?, the alarm will operate in the interrupt mode, where an active low pulse width of 250ms will appear at the irq /f out pin when the rtc is triggered by the alarm, as defined by the alarm registers (0ch to 11h). when the im bit is cleared to ?0?, the alarm will operate in standard mode, where the irq /f out pin will be set low until the alm status bit is cleared to ?0?. frequency output and interrupt bit (fobatb) this bit enables/disables the irq /f out pin during battery-backup mode (i.e. v bat power source active). when the fobatb is set to ?1?, the irq /f out pin is disabled during battery-backup mode. this means that both the frequency output and alarm ou tput functions are disabled. when the fobatb is cleared to ?0?, the irq /f out pin is enabled during battery-backup mode. note that the open drain irq /f out pin will need a pull-up to the battery voltage to operate in battery-backup mode. frequency out control bits (fo<3:0>) these bits enable/disable the frequency output function and select the output frequency at the irq /f out pin. see table 5 for frequency selection. default for the isl12022 is fo<3:0> = 1h, or 32.768khz output. when the frequency mode is enabled, it will override the alarm mode at the irq /f out pin. table 3. interrupt control register (int) addr7 6 5 4 3210 08h arst wrtc im fobatb fo3 fo2 fo1 fo0 table 4. im bit interrupt/alarm frequency 0 single time event set by alarm 1 repetitive/recurring time event set by alarm isl12022
15 fn6659.2 june 23, 2009 power supply control register (pwr_vdd) clear time stamp bit (clrts) this bit clears time stamp v dd to battery (tsv2b) and time stamp battery to v dd registers (tsb2v). the default setting is 0 (clrts = 0) and the enabled setting is 1 (clrts = 1). v dd brownout trip voltage bits (v dd trip<2:0) these bits set the 6 trip levels for the v dd alarm, indicating that v dd has dropped below a preset le vel. in this event, the lvdd bit in the status register is set to ?1?. see table 6. battery voltage trip voltage register (pwr_vbat) this register controls the trip points for the two v bat alarms, with levels set to approximately 85% and 75% of the nominal battery level. reseal bit (resealb) this is the reseal bit for actively disconnecting v bat pin from the internal circuitry. setting this bit allows the device to disconnect the battery and elim inate standby current drain while the device is unused. once v dd is powered up, this bit is reset and the v bat pin is then connected to the internal circuitry. the application for this bit involves placing the chip on a board with a battery and testing the board. once the board is tested and ready to ship, it is desirable to disconnect the battery to keep it fresh until the board or unit is placed into final use. setting resealb = ?1? initiates the battery disconnect, and after v dd power is cycled down and up again, the reseal bit is cleared to ?0?. battery level monitor tr ip bits (vb85tp<2:0>) three bits select the first alarm (85% of nominal v bat ) level for the battery voltage monitor. there are total of 7 levels that could be selected for the first alarm. any of the of levels could be selected as the first alarm with no reference as to nominal battery voltage level. see table 8. battery level monitor tr ip bits (vb75tp<2:0>) three bits select the second alarm (75% of nominal v bat ) level for the battery voltage monito r. there are total of 7 levels that could be selected for the seco nd alarm. any of the of levels could be selected as the second alarm with no reference as to nominal battery voltage level. see table 9. table 5. frequency selection of irq/f out pin frequency, f out units fo3 fo2 fo1 fo0 0 hz0 000 32768 hz 0 0 0 1 4096 hz 0 0 1 0 1024 hz 0 0 1 1 64 hz0 100 32 hz0 101 16 hz0 110 8 hz0 111 4 hz1 000 2 hz1 001 1 hz1 010 1/2 hz1 011 1/4 hz1 100 1/8 hz1 101 1/16 hz 1 1 1 0 1/32 hz 1 1 1 1 addr 7 6543 2 1 0 09h clrts 0 0 0 0 v dd trip2 v dd trip1 v dd trip0 table 6. v dd trip levels v dd trip2 v dd trip1 v dd trip0 trip voltage (v) 0002.295 0012.550 0102.805 0113.060 1004.250 1014.675 table 7. addr 7 6 5 4 3 2 1 0 0ah d resealb vb85tp2 vb85tp1 vb85tp0 vb75tp2 vb75tp1 vb75tp0 table 8. vb85t alarm level vb85tp2 vb85tp1 vb85tp0 battery alarm trip level (v) 0 0 0 2.125 0 0 1 2.295 0 1 0 2.550 0 1 1 2.805 1 0 0 3.060 1 0 1 4.250 1 1 0 4.675 isl12022
16 fn6659.2 june 23, 2009 initial at and dt setting register (itro) these bits are used to trim the initial error (at room temperature) of the crystal. both digital trimming (dt) and analog trimming (at) methods are available. the digital trimming uses clock pulse skipping and insertion for frequency adjustment. analog trimming uses load capacitance adjustment to pull the oscillator frequency. a range of +62.5ppm to -61.5ppm is possible with combined digital and analog trimming. aging and initial trim digital trimming bits (idtr0<1:0>) these bits allow 30.5ppm initial trimming range for the crystal frequency. this is meant to be a coarse adjustment if the range needed is outside t hat of the iatr control. see table 10. the idtr0 register should only be changed while the tse (temp sense enable) bit is ?0?. aging and initial analog trimming bits (iatr0 <5:0>) the analog trimming register allows +32ppm to -31ppm adjustment in 1ppm/bit increments. this enables fine frequency adjustment for trimming initial crystal accuracy error or to correct for aging drift. the iatr0 register should only be changed while the tse (temp sense enable) bit is ?0?. aging adjustment is normally a few ppm and can be handled by writing to the iatr section. table 9. battery level monitor trip bits (vb75tp<2:0>) vb75tp2 vb75tp1 vb75tp0 battery alarm trip level (v) 0 0 0 1.875 0 0 1 2.025 0 1 0 2.250 0 1 1 2.475 1 0 0 2.700 1 0 1 3.750 1 1 0 4.125 table 10. idtr0 trimming range idtr01 idtr00 trimming range 0 0 default/disabled 0 1 +30.5ppm 1 0 0ppm 1 1 -30.5ppm table 11. initial at and dt setting register addr 7 6 543210 0bh idtr01 idtr00 iatr05 iatr04 iatr03 iatr02 iatr01 iatr00 table 12. iatr0 trimming range iatr05 iatr04 iatr03 iatr02 iatr01 iatr00 trimming range 000000 +32 000001 +31 000010 +30 000011 +29 000100 +28 000101 +27 000110 +26 000111 +25 001000 +24 001001 +23 001010 +22 001011 +21 001100 +20 001101 +19 001110 +18 001111 +17 010000 +16 010001 +15 010010 +14 010011 +13 010100 +12 010101 +11 010110 +10 010111 +9 011000 +8 011001 +7 011010 +6 011011 +5 011100 +4 011101 +3 011110 +2 011111 +1 100000 0 100001 -1 100010 -2 100011 -3 100100 -4 100101 -5 100110 -6 100111 -7 101000 -8 101001 -9 101010 -10 101011 -11 101100 -12 101101 -13 101110 -14 101111 -15 110000 -16 110001 -17 isl12022
17 fn6659.2 june 23, 2009 note that setting the iatr to the lowest settings (-31ppm) with the default 32khz output can cause the oscillator frequency to become unstable on power-up. the lowest settings for iatr should be avoided to insure oscillator frequency integrity. if the lowe st iatr settings are needed, then the user is advised to disable the f out and enable again to insure placing the oscillator in a stable condition. alpha register (alpha) the alpha variable is 8 bits and is defined as the temperature coefficient of crystal from -40c to t0, or the alpha cold (there is an alpha hot register that must be programmed as well). it is normally given in units of ppm/c 2 , with a typical value of -0.034. the isl12022 device uses a scaled version of the absolute value of this coefficient in order to get an integer value. therefore, alpha<7:0> is defined as the (|actual alpha value| x 2048) and converted to binary. for example, a crystal with alpha of -0.034ppm/c 2 is first scaled (|2048*(-0.034)| = 70d) and then converted to a binary number of 01000110b. the practical range of actual alpha values is from -0.020 to -0.060. the alpha register should only be changed while the tse (temp sense enable) bit is ?0?. note that both the alpha and the alpha hot registers need to be programmed with values for full range temperature compensation. beta register (beta) temperature sensor enabled bit (tse) this bit enables the temperature sensing operation, including the temperature sensor, a/d c onverter and at/dt register adjustment. the default mode after power-up is disabled (tse = 0). to enable the operation, tse should be set to 1 (tse = 1). when the temperature sensor is disabled, the initial values for iatr and idtr registers are used for frequency control. all changes to the idtr, iatr , alpha and beta registers must be made with tse = 0. after loading the new values, tse can be enabled and the new values are used. when tse is set to 1, the temperature conversion cycle begins and will end when two temperature conv ersions are completed. the average of the two conversions is in the temp registers. the total time for temperature sense and conversion is approximately 22ms from the time tse = 1 write is completed. temp sensor conversion in battery mode bit (btse) this bit enables the temperat ure sensing and correction in battery mode. btse = 0 (def ault) no conversion, temp sensing or compensation in battery mode. btse = 1 indicates temp sensing and compensation enabled in battery mode. the btse is disabled when the battery voltage is lower than 2.7v. no temperature compensation will take place with v bat <2.7v. frequency of temperature sensing and correction bit (btsr) this bit controls the frequency of temperature sensing and correction. btsr = 0 default mode is every 10 minutes, btsr = 1 is every 1.0 minute. note that btse has to be enabled in both cases. see table 15. the temperature meas urement conversion time is the same for battery mode as for v dd mode, approximately 22ms. the battery mode current will increas e during this conversion time to typically 68a. the average in crease in battery current is much lower than this due to the small duty cycle of the on-time versus off-time for the conversion. to figure the average increase in battery current, we take the the change in current times th e duty cycle. for the 1 minute temperature period the aver age current is shown in equation 1: 110010 -18 110011 -19 110100 -20 110101 -21 110110 -22 110111 -23 111000 -24 111001 -25 111010 -26 111011 -27 111100 -28 111101 -29 111110 -30 111111 -31 table 13. alpha register addr 7 6 5 4 3 2 1 0 0ch d alpha6 alpha5 alpha4 alpha3 alpha2 alpha1 alpha0 table 14. addr76543210 0dh tse btse btsr beta4 beta3 beta2 beta1 beta0 table 12. iatr0 trimming range (continued) iatr05 iatr04 iatr03 iatr02 iatr01 iatr00 trimming range table 15. frequency of temperature sensing and correction bit btse btsr tc period in battery mode 00 off 01 off 1 0 10 minutes 1 1 1 minute i bat 0.022s 60s ----------------- - = 68 a 250na = (eq. 1) isl12022
18 fn6659.2 june 23, 2009 for the 10 minute temperature period the average current is shown in equation 2: if the application has a stable temperature environment that doesn?t change quickly, the 10 minute option will work well and the backup battery lifetime impact is minimized. if quick temperature vari ations are expected (mult iple cycles of more than 10 within an hour), then the 1 minute option should be considered and the slightly higher battery current figured into overall battery life. gain factor of at bit (beta<4:0>) beta is specified to take care of the cm variations of the crystal. most crystals specify cm around 2.2ff. for example, if cm > 2.2ff, the actual at steps may reduce from 1ppm/step to approximately 0.8 0ppm/step. beta is then used to adjust for this variation and restore the step size to 1ppm/step. beta values are limited in the range from 01000 to 11111 as shown in table 16 . to use table 16, the device is tested at two at settings as shown in equation 3: where: at(max) = f out in ppm (at at = 00h) and at(min) = f out in ppm (at at = 3fh). the beta values result is indexed in the right hand column and the resulting beta factor (for the register) is in the same row in the left column. the value for beta should only be changed while the tse (temperature sense enable) bit is ?0?. the procedure for writing the beta register involves two steps. first, write the new value of beta with tse = 0. then write the same value of beta with tse = 1. this will insure the next temperature sense cycle will use the new beta value. final analog trimming register (fatr) this register shows the final setting of at after temperature correction. it is read-only; the us er cannot overwrite a value to this register. this value is accessible as a means of monitoring the temperature compensati on function. see table 17. final digital trimmi ng register (fdtr) this register shows the final se tting of dt after temperature correction. it is read-only; the user cannot overwrite a value to this register. the value is accessible as a means of monitoring the temperature compensation function. the corresponding clock adjustment values are shown in table 19. the dt setting ha s both positive and negative settings to adjust for any offset in the crystal. . table 16. beta values beta<4:0> at step adjustment 01000 0.5000 00111 0.5625 00110 0.6250 00101 0.6875 00100 0.7500 00011 0.8125 00010 0.8750 00001 0.9375 00000 1.0000 10000 1.0625 10001 1.1250 i bat 0.022s 600s ----------------- - = 68 a 25na = (eq. 2) betavalues at max () at min () ? () /63 = (eq. 3) 10010 1.1875 10011 1.2500 10100 1.3125 10101 1.3750 10110 1.4375 10111 1.5000 11000 1.5625 11001 1.6250 11010 1.6875 11011 1.7500 11100 1.8125 11101 1.8750 11110 1.9375 11111 2.0000 table 17. final analog trimming register addr 7 6 5 4 3 2 1 0 0eh 0 0 fatr5 fatr4 fatr3 fatr2 fatr1 fatr0 table 18. final digital trimming register addr 7 6 5 4 3 2 1 0 0fh 0 0 0 fdtr4 fdtr3 fdtr2 fdtr1 fdtr0 table 19. clock adjustment values for final digital trimming register fdtr<2:0> decimal ppm adjustment 00000 0 0 00001 1 30.5 00010 2 61 table 16. beta values (continued) beta<4:0> at step adjustment isl12022
19 fn6659.2 june 23, 2009 alarm registers (10h to 15h) the alarm register bytes are set up identical to the rtc register bytes, except that th e msb of each byte functions as an enable bit (enable = ?1?). these enable bits specify which alarm registers (seconds, minu tes, etc.) are used to make the comparison. note that there is no alarm byte for year. the alarm function works as a comparison between the alarm registers and the rtc register s. as the rtc advances, the alarm will be triggered once a match occurs between the alarm registers and the rtc registers. any one alarm register, multiple registers, or all regi sters can be enabled for a match. there are two alarm operation modes: single event and periodic interrupt mode: ? single event mode is enabled by setting the bit 7 on any of the alarm registers (esca0... edwa0) to ?1?, the im bit to ?0?, and disabling the frequency output. this mode permits a one-time match between the alarm registers and the rtc registers. once this match occurs, the alm bit is set to ?1? and the irq /f out output will be pulled low and will remain low until the alm bit is reset. this can be done manually or by usi ng the auto-reset feature. ? interrupt mode is enabled by setting the bit 7 on any of the alarm registers (esca0... ed wa0) to ?1?, the im bit to ?1?, and disabling the frequency output. the irq /f out output will now be pulsed each time an alarm occurs. this means that once the interrupt mode alarm is set, it will continue to alarm for each occurring match of the alarm and present time. this mode is convenient for hourly or daily hardware interrupts in microcontroller applications such as security cameras or utility meter reading. to clear a single event alarm, the alm bit in the status register must be set to ?0? with a write. note that if the arst bit is set to 1 (address 08h, bit 7), the alm bit will automatically be cleared when the status register is read. following are examples of both single event and periodic interrupt mode alarms. example 1 ? alarm set with single interrupt (im = ?0?) ? a single alarm will occur on january 1 at 11:30 a.m. ? set alarm registers as follows: after these registers are set, an alarm will be generated when the rtc advances to exactly 11:30 a.m. on january 1 (after seconds changes from 59 to 00) by setting the alm bit in the status register to ?1? and also bringing the irq /f out output low. example 2 ? pulsed interrupt once per minute (im = ?1?) ? interrupts at one minute intervals when the seconds register is at 30s. ? set alarm registers as follows: 00011 3 91.5 00100 4 122 00101 5 152.5 00110 6 183 00111 7 213.5 01000 8 244 01001 9 274.5 01010 10 305 10000 0 0 10001 -1 -30.5 10010 -2 -61 10011 -3 -91.5 10100 -4 -122 10101 -5 -152.5 10110 -6 -183 10111 -7 -213.5 11000 -8 -244 11001 -9 -274.5 11010 -10 -305 table 19. clock adjustment values for final digital trimming register (continued) fdtr<2:0> decimal ppm adjustment alarm register bit description 76543210hex sca0 00000000 00hsec onds disabled mna0 10110000 b0hminutes set to 30, enabled hra0 10010001 91hhours set to 11, enabled dta0 10000001 81hdate set to 1, enabled moa0 10000001 81hmonth set to 1, enabled dwa0 00000000 00hday of week disabled alarm register bit description 76543210hex sca0 10110000b0hsec onds set to 30, enabled mna0 00000000 00hminutes disabled hra0 00000000 00hhours disabled dta0 00000000 00hdate disabled moa0 00000000 00hmonth disabled dwa0 00000000 00hday of week disabled isl12022
20 fn6659.2 june 23, 2009 once the registers are set, the following waveform will be seen at irq /f out : note that the status register alm bit will be set each time the alarm is triggered, but does not need to be read or cleared. time stamp v dd to battery registers (tsv2b) the tsv2b register bytes are identical to the rtc register bytes, except they do not extend beyond the month. the time stamp captures the first v dd to battery voltage transition time, and will not update upon subsequent events, until cleared (only the first event is captured before clearing). set clrts = 1 to clear this register (add 09h, pwr_v dd register). note that the time stamp registers are cleared to all ?0?, including the month and day, which is different from the rtc and alarm registers (those registers default to 01h). this is the indicator that no time stamping has occurred since the last clear or initial power-up. once a time stamp occurs, there will be a non-zero time stamp. time stamp battery to v dd registers (tsb2v) the time stamp battery to v dd register bytes are identical to the rtc register bytes, exce pt they do not extend beyond month. the time stamp captures the last transition of v bat to v d (only the last event of a series of power-up/down events is retained). set clrts = 1 to clear this register (add 09h, pwr_v dd register). dst control registers (dstcr) 8 bytes of control registers have been assigned for the daylight savings time (dst) functions. dst beginning (set forward) time is controlled by the registers dstmofd, dstdwfd, dstdtfd, and dsthrfd. dst ending time (set backward or reverse) is controlled by dstmorv, dstdwrv, dstdtrv and dsthrrv. tables 20 and 21 describe the st ructure and functions of the dstcr. dst forward registers (20h to 23h) dst forward is controlled by the following dst registers: dst enable dste is the dst enabling bit located in bit 7 of register 20h (dstmofdxx). set dste = 1 wil l enable the dste function. upon powering up for the first time (including battery), the dste bit defaults to ?0?. when dste is set to ?1? the rtc time must be at least one hour before the scheduled dst time change for the correction to take place. when dste is set to ?0?, the dstadj bi t in the status register automatically resets to ?0?. dst month forward dstmofd sets the month that dst starts. the format is the same as for the rtc register month, from 1 to 12. the default value for the dst begin month is 00h. 60s rtc and alarm registers are both ?30s? figure 13. irq /f out waveform table 20. dst forward registers address function 7 6 5 43210 20h month forward dste 0 0 mofd20 mofd13 mofd12 mofd11 mofd10 21h day forward 0 dwfde wkfd12 wkfd11 wkfd10 dwfd12 dwfd11 dwfd10 22h date forward 0 0 dtfd21 dtfd20 dtfd13 dtfd12 dtfd11 dtfd10 23h hour forward 0 0 hrfd21 hrfd20 hrfd13 hrfd12 hrfd11 hrfd10 table 21. dst reverse registers address name 7 6 5 4 3 2 1 0 24h month reverse 0 0 0 morv20 morv13 morv12 morv11 morv10 25h day reverse 0 dwrve wkrv12 wkrv11 wk rv10 dwrv12 dwrv11 dwrv10 26h date reverse 0 0 dtrv21 dtrv20 dtrv13 dtrv12 dtrv11 dtrv10 27h hour reverse 0 0 hrrv21 hrrv20 hrrv13 hrrv12 hrrv11 hrrv10 isl12022
21 fn6659.2 june 23, 2009 dst day/week forward dstdwfd contains both the day of the week and the week of the month data for dst forward control. dst can be controlled either by actual date or by setting both the week of the month and the day of the week. dstdwfde sets the priority of the day/week over the date. for dstdwfde = 1, day/week is the priority. you must have the correct day of week entered in the rtc registers for the day/week correction to work properly. ? bits 0,1,2 contain the day of the week information which sets the day of the week that dst starts. note that day of the week counts from 0 to 6, like the rtc registers. the default for the dst forward day of the week is 00h (normally sunday). ? bits 3, 4, 5 contain the week of the month information that sets the week that dst starts. the range is from 1 to 5, and week 7 is used to indicate the last week of the month. the default for the dst forward week of the month is 00h. dst date forward dstdtfd controls which date dst begins. the format for the date is the same as for the rtc register, from 1 to 31. the default value for dst forward date is 00h. dstdtfd is only effective if dstdwfde = 0. dst hour forward dsthrfd controls the hour that dst begins. the rtc hour and dsthrfd registers have the same formats except there is no military bit for dst hour. the user sets the dst hour with the same format as used for the rtc hour (am/pm or mil) but without the mil bit, a nd the dst will still advance as if the mil bit were there. the default value for dst hour forward is 00h. dst reverse registers (24h to 27h) dst end (reverse) is controlled by the following dst registers: dst month reverse dstmorv sets the month that dst ends. the format is the same as for the rtc register month, from 1 to 12. the default value for the dst e nd month is october (10h). dst day/week reverse dstdwrv contains both the day of the week and the week of the month data for dst reverse control. dst can be controlled either by actual date or by setting both the week of the month and the day of the week. dstdwrve sets the priority of the day/week over the date. for dstdwrve = 1, day/week is the priority. you must have the correct day of week entered in the rtc registers for the day/week correction to work properly. ? bits 0,1,2 contain the day of the week information which sets the day of the week that dst ends. note that day of the week counts from 0 to 6, like the rtc registers. the default for the dst reverse day of the week is 00h (normally sunday). ? bits 3, 4, 5 contain the week of the month information that sets the week that dst ends. the range is from 1 to 5, and week 7 is used to indicate the last week of the month. the default for the dst reverse week of the month is 00h. dst date reverse dstdtrv controls which date dst ends. the format for the date is the same as for the rtc register, from 1 to 31. the default value for dst date reverse is 00h. the dstdtrv is only effective if the dwrve = 0. dst hour reverse dsthrrv controls the hour that dst ends. the rtc hour and dsthrfd registers have the same formats except there is no military bit for dst hour. the user sets the dst hour with the same format as used for the rtc hour (am/pm or mil) but without the mil bit, and the dst will still advance as if the mil bit were there. the default value for dst hour reverse is 00h. temp registers (temp) the temperature sensor produc es an analog voltage output which is input to an a/d c onverter and produces a 10-bit temperature value in degrees kelvin. tk07:00 are the lsbs of the code, and tk09:08 are the msbs of the code. the temperature result is actually the average of two successive temperature measurements to pr oduce greater resolution for the temperature control. the output code can be converted to degrees centigrade (c) by first converting from binary to decimal, dividing by 2, and t hen subtracting 273d, as shown in equation 4: the practical range for the temp sensor register output is from 446d to 726d, or -50c to +90c. the temperature compensation function is only guaranteed over -40c to +85c. the tse bit must be set to ?1? to enable temperature sensing. nppm registers (nppm) the nppm value is exactly 2x the net correction required to bring the oscillator to 0ppm error. the value is the combination of oscillator initial correction (ippm) and crystal temperature dependent correction (cppm). ippm is used to compensate the oscillator offset at room temperature and is controlled by the itr0 and beta registers, which are fixed during factor test. table 22. temp 76543210 tk0l tk07 tk06 tk05 tk04 tk03 tk02 tk01 tk00 tk0m000000tk09tk08 temperature in c [(tk <9:0>)/2] - 273 = (eq. 4) isl12022
22 fn6659.2 june 23, 2009 the cppm compensates the oscillator frequency fluctuation over temperature. it is dete rmined by the temperature (t), crystal curvature parameter (a lpha), and crystal turnover temperature (xt0). t is the result of the temp sensor/adc conversion, whose decimal re sult is 2x the actual temperature in kelvin. alpha is from either the alpha (cold) or alphah (hot) register depending on t, and xt0 is from the xt0 register. nppm is governed by equation 5: nppm = ippm(itr0,beta) + alpha x (t-t0) 2 where: t is the reading of the adc, re sult is 2 x temperature in degrees kelvin. or note that nppm can also be predicted from the fatr and fdtr register by the relationship (all values in decimal): nppm = 2*(beta*fatr - (fdtr-16)) xt0 registers (xt0) turnover temperature (xt<3:0>) the apex of the alpha curve occurs at a point called the turnover temperature, or xt 0. crystals normally have a turnover temperature between +20c and +30c, with most occurring near +25c. the isl12022 allows setting the turnover temperature so that temperature compensation can more exactly fit the curve of a crystal. table 24 shows the values available, with a range from +17.5c to +32.5c in +0.5c increments. the default value is 00000b or +25c. alpha hot register (alphah) the alpha hot variable is 7 bits and is defined as the temperature coefficient of crysta l from the t0 value to +85c. (both alpha hot and alpha cold must be programmed to provide full temperature compen sation). it is normally given in units of ppm/c 2 ,with a typical value of -0.034. like the alpha cold version, a scaled version of the absolute value of this coefficient is used in order to get an integer value. therefore, alphah<7:0> is defined as the (|actual alphah value| x 2048) and converted to binary. for ex ample, a crystal with alphah of -0.034ppm/c 2 is first scaled (|2048*(-0.034)| = 70d) and then converted to a binary number of 0100110b. table 23. turnover temperature addr76543210 2ch 0 0 0 xt4 xt3 xt2 xt1 xt0 table 24. xt0 values xt<4:0> turnover temperature 01111 32.5 01110 32.0 01101 31.5 01100 31 01011 30.5 01010 30 nppm ippm cppm + = nppm ippm alpha t t0 ? () ? 2 4096 --------------------------------------------------- - + = (eq. 5) alpha 2048 ? = t 2 298 ? () xt0 + = (eq. 6) t 596 xt0 + = 01001 29.5 01000 29.0 00111 28.5 00110 28.0 00101 27.5 00100 27.0 00011 26.5 00010 26.0 00001 25.5 00000 25.0 10000 25.0 10001 24.5 10010 24.0 10011 23.5 10100 23.0 10101 22.5 10110 22.0 10111 21.5 11000 21.0 11001 20.5 11010 20.0 11011 19.5 11100 19.0 11101 18.5 11110 18.0 11111 17.5 table 25. alphah register addr 76543210 2dh d alp_h6 alp_h5 alp_h4 alp_h3 alp_h2 alp_h1 alp_h0 table 24. xt0 values (continued) xt<4:0> turnover temperature isl12022
23 fn6659.2 june 23, 2009 the practical range of actual alphah values is from -0.020 to -0.060. the alphah register should only be changed while the tse (temp sense enable) bit is ?0?. user registers (acce ssed by using slave address 1010111x) addresses [00h to 7fh] these registers are 128 bytes of battery-backed user sram. i 2 c serial interface the isl12022 supports a bi-directional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlli ng the transfer is the master and the device being controlled is the slave. the master always initiates data transfers and provides the clock for both transmit and receive op erations. therefore, the isl12022 operates as a slave device in all applications. all communication over the i 2 c interface is conducted by sending the msb of each byte of data first. protocol conventions data states on the sda line can change only during scl low periods. sda state changes during scl high are reserved for indicating start and stop conditions (see figure 14). on power-up of the isl12022, the sda pin is in the input mode. all i 2 c interface operations must begin with a start condition, which is a high to low transition of sda while scl is high. the isl12022 continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition is met (see figure 14). a start condition is ignored during the power-up sequence. all i 2 c interface operations must be terminated by a stop condition, which is a low to high transition of sda while scl is high (see figure 14). a stop condition at the end of a read operation or at the end of a write operation to memory only places the device in its standby mode. an acknowledge (ack) is a software convention used to indicate a successful data transfer. the transmitting device, either master or slave, releases the sda bus after transmitting eight bits. during the ninth clock cycle, the receiver pulls the sda line low to acknowledge the reception of the 8 bits of data (see figure 15). figure 14. valid data changes, start and stop conditions figure 15. acknowledge response from receiver sda scl start data data stop stable change data stable sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high impedance high impedance isl12022
24 fn6659.2 june 23, 2009 the isl12022 responds with an ack after recognition of a start condition followed by a valid identification byte, and once again, after successful receipt of an address byte. the isl12022 also responds with an ack after receiving a data byte of a write operation. t he master must respond with an ack after receiving a data byte of a read operation. device addressing following a start condition, the master must output a slave address byte. the 7 msbs are the device identifiers. these bits are ?1101111? for the rtc registers and ?1010111? for the user sram. the last bit of the slave address byte defines a read or write operation to be performed. when this r/w bit is a ?1?, a read operation is selected. a ?0? selects a write operation (refer to figure 17). after loading the entire slave address byte from the sda bus, the isl12022 compares the device identifier and device select bits with ?1101111? or ?1010111?. upon a correct compare, the device outputs an acknowledge on the sda line. following the slave byte is a one byte word address. the word address is either supplied by the master device or obtained from an internal counter. on power-up, the internal address counter is set to address 00h, so a current address read starts at address 00h. when required, as part of a random read, the master must supply the 1 word address bytes, as shown in figure 20. in a random read operation, the slave byte in the ?dummy write? portion must match the slave byte in the ?read? section. for a random read of the control/stat us registers, the slave byte must be ?1101111x? in both places. write operation a write operation requires a star t condition, followed by a valid identification byte, a valid address byte, a data byte, and a stop condition. after each of the three bytes, the isl12022 responds with an ack. at this time, the i 2 c interface enters a standby state. read operation a read operation consists of a th ree byte instruction, followed by one or more data bytes (see fi gure 20). the master initiates the operation issuing the following sequence: a start, the identification by te with the r/w bit set to ?0?, an address byte, a second start, and a second identification byte with the r/w bit set to ?1?. after each of the three bytes, the isl12022 responds with an ack. then the isl12022 transmits data bytes as long as the master responds with an ack during the scl cycle following the eighth bit of each byte. the master terminates the read operation (issuing a stop condition) following the last bit of the last data byte (see figure 20). the data bytes are from the memory location indicated by an internal pointer. this pointer?s initial value is determined by the address byte in the read operation instruction, and increments by one during transmission of each data byte. after reaching the memory location 2fh, the pointer ?rolls over? to 00h, and the device continues to output data for each ack received. figure 16. byte write sequence (slave address for csr shown) s t a r t s t o p identification byte data byte a c k signals from the master signals from the isl12022 a c k 10 0 11 a c k write signal at sda 0000 111 address byte figure 17. slave address, word address, and data bytes slave address byte d7 d6 d5 d2 d4 d3 d1 d0 a0 a7 a2 a4 a3 a1 data byte a6 a5 1 10 1 1 1 r/w 1 word address table 26. suggested surface mount crystals manufacturer part number citizen cm200s epson mc-405, mc-406 raltron rsm-200s saronix 32s12 ecliptek ecpsm29t-32.768k ecs ecx-306 fox fsm-327 isl12022
25 fn6659.2 june 23, 2009 application section battery-backup details the isl12022 has automatic swit chover to battery-backup when the v dd drops below the vbat mode threshold. a wide variety of backup sources can be used, including standard and rechargeable lithium, super capacitors, or regulated secondary sources. the serial interface is disabled in battery-backup, while the oscillator and rtc registers are operational. the sram register contents are powered to preserve their contents as well. the input voltage range for v bat is 1.8v to 5.5v, but keep in mind the temperature compensation only operates for v bat > 2.7v. note that the device is not guaranteed to operate with a v bat < 1.8v, so the battery should be changed before discharging to that level. it is strongly advised to monitor the low battery indicators in the status registers and take action to replace discharged batteries. if a supercapacitor is used, it is possible that it may discharge to below 1.8v during prolonged power-down. once powered up, the device may lose serial bus communications until both v dd and v bat are powered down together. to avoid that situation, including situations where a battery may discharge deeply, the circuit in figure 18 can be used. the diode, d bat will add a small drop to the battery voltage but will protect the circuit should battery voltage drop below 1.8v. the jumper is added as a safeguard should the battery ever need to be disconnect from the circuit. the v dd negative slew rate should be limited to below the data sheet spec (10v/ms) otherwise battery switchover can be delayed, resulting in sram contents corruption and oscillator operation interruption. some applications will require separate supplies for the rtc v dd and the i 2 c pull-ups. this is not advised, as it may compromise the operation of the i 2 c bus. for applications that do require serial bus communication with the rtc v dd powered down, the sda pin must be pulled low during the time the rtc v dd ramps down to 0v. otherwise, the device may lose serial bus co mmunications once v dd is powered up, and will return to normal operation only once v dd and v bat are both powered down together. oscillator crys tal requirements the isl12022 uses a standard 32.768khz crystal. either through hole or surface mount cr ystals can be used. table 26 lists some recommended surface mount crystals and the parameters of each. this list is not exhaustive and other surface mount devices can be used with the isl12022 if their specifications are very similar to the devices listed. the crystal should have a required parallel load capacitance of 12.5pf and an equivalent series resistance of less than 50k. the crystal?s temperature range specification should match the application. many crystals are rated for -10c to +60c (especially through-hole and tuning fork types), so an appropriate crystal should be selected if extended temperature range is required. layout considerations the crystal input at x1 has a very high impedance, and oscillator circuits operatin g at low frequencies (such as 32.768khz) are known to pick up noise very easily if layout precautions are not followed. most instances of erratic clocking or large accuracy errors can be traced to the susceptibility of the oscillator circuit to interf erence from adjacent high speed clock or data lines. careful layout of the rtc circuit will avoid noise pickup and insure accurate clocking. figure 19 shows a suggested layout for the isl12022 device using a surface mount crystal. two main precautions should be followed: ? do not run the serial bus lines or any high speed logic lines in the vicinity of the crystal. these logic level lines can induce noise in the oscillator circuit, causing misclocking. ? add a ground trace around the crystal with one end terminated at the chip ground. this will provide termination for emitted noise in the vicinity of the rtc device. in addition, it is a good idea to avoid a ground plane under the x1 and x2 pins and the crystal, as this will affect the load capacitance and therefore the oscillator accuracy of the circuit. if the ~irq /f out pin is used as a clock, it should be routed away from the rtc device as well. the traces for the v bat and v dd pins can be treated as a ground, and should be routed around the crystal. applications information crystal oscillator frequency compensation crystal characteristics the isl12022 device contains a complete system for adjusting the frequency of the crystal oscillator to figure 18. suggested battery-backup circuit d bat c bat c in bat43w 0.1f 0.1f v dd = 2.7v to 5.5v v bat = 1.8v to 3.2v j bat isl12022 vdd gnd vbat + figure 19. suggested layout for isl12022 and crystal isl12022
26 fn6659.2 june 23, 2009 compensate for temperature va riation. a typical 32.768khz crystal used with rtc devices has a temperature versus frequency curve, as shown in figure 21. the curve in figure 21 follows equation 7: where is the temperature constant, with a typical value of 0.034 ppm/c. t 0 is the turnover temperature of the crystal, which is the apex of the parabolic curve. if the two factors and t 0 are known, it is possible to correct for crystal temperature error to very high accuracy. the crystal will have an initial accuracy error at room temperature, typically spec ified at 20c. the other important characteristic is the capacitances associated with the crystal. the load capacitance is normally specified at 12.5pf, although it can be lower in some cases. there is also a motional capacitance which affects the ability of the load capacitance to pull the oscillation frequency, and it is usually in the range of 2.2ff to 4.0ff. rtc clock control the isl12022 uses two mechanisms to adjust the rtc clock and correct for the temper ature error of the external crystal. the analog trimming (at) adjusts the load capacitance seen by the crystal. analog sw itches connect the appropriate capacitance to change the frequency in increments of 1ppm. the adjustment range for the isl12022 is +32/-31ppm. the at can be further refined using the beta register. the beta register function is to allow for changes in c m (motional capacitance) which will affect the incremental frequency change of the at adjustment. a simple test procedure uses the beta register to bring the step size back to 1ppm. normally, the crystal frequency is adjusted at room temperature to zero out the frequency error using the iatrxx register bits (initial analog trimming). in addition, the iatrxx setting is varied up and down to record the variation in oscillator frequency compared to the step change in iatrxx. once that value is known then the beta register is used to adjust the step size to be as close to 1ppm per iatrxx step as possible. after that adjustment is made, then any isl12022 temperature compensation adjustments will use a 1ppm change for each bit change in the internal at adjustment. the digital trimming (dt) uses clock pulse add/subtract logic to change the rtc timing during temperature compensation. the dt steps are much coarser than the at steps and are therefore used fo r large adjustments. the dt steps are 30.5ppm, and the ra nge is from -305ppm to +305ppm. the frequency output function will show the clock variation with dt settings, except for the 32,768hz setting which only shows the at control. active temperature compensation the isl12022 contains an intelligent logic circuit which takes the temperature sensor digita l value as the only input variable. it then uses the register values for the crystal variables and t 0 , and combines those with calibration from the beta and itr0 registers to produce ?final? values for the at and dt, known as fatr (final at register) and fdtr (final dt register). those at and dt values combine to directly compensate for the temperature error shown in figure 21. the temperature sensor produces a new value every 60s (or up to 10 minutes in battery mode), which triggers the logic to calculate a new at/dt value set. for every temperature calculation result, there can only be one corresponding at/dt correction value. figure 20. read sequence (csr slave address shown) signals from the master signals from the slave signal at sda s t a r t identification byte with r/w = 0 address byte a c k a c k 0 s t o p a c k 1 identification byte with r/w = 1 a c k s t a r t last read data byte first read data byte a c k 10 1 1111 10 1 11 11 temperature (c) -160 -140 -120 -100 -80 -60 -40 -20 0 -40-30-20-10 0 1020304050607080 ppm figure 21. rtc crystal temperature drift f t ( t 0 ) 2 ? ? = (eq. 7) isl12022
27 fn6659.2 june 23, 2009 measuring oscillator accuracy the best way to analyze the isl12022 frequency accuracy is to set the irq /f out pin for a specific frequency, and look at the output of that pin on a high accuracy frequency counter (at least 7 digits accuracy). note that the irq /f out is a drain output and will require a pull-up resistor. using the 1.0hz output frequen cy is the most convenient as the ppm error is as expressed in equation 8: other frequencies may be used for measurement but the error calculation be comes more complex. when the proper layout guid elines are observed, the oscillator should start up in most circuits in less than 1s. when testing rtc circuits, a common impulse is to apply a scope probe to the circuit at the x2 pin (oscillator output) and observe the waveform. do not do this! although in some cases you may see a usable waveform, due to the parasitics (usually 10pf to ground) applie d with the scope probe, there will be no useful information in that waveform other than the fact that the circuit is oscillating. the x2 output is sensitive to capacitive impedance so the voltage levels and the frequency will be affected by the parasitic elements in the scope probe. use the f out output and a frequency counter for the most accurate results. temperature compensation operation the isl12022 temperature com pensation feature needs to be enabled by the user. this must be done in a specific order as follows. 1. read register 0dh, the beta register. this register contains the 5-bit beta trimmed value which is automatically loaded on initia l power-up. mask off the 5lsb?s of the va lue just read. 2. bit 7 of the beta register is the master enable control for temperature sense operation. set this to ?1? to allow continuous temperature fr equency correction. frequency correction will then happen every 60s with v dd applied. 3. bits 5 and 6 of the beta r egister control temperature compensation in battery-backup mode (see table 15). set the values for the operation desired. 4. write back to register 0dh making sure not to change the 5 lsb values, and include the desired compensation control bits. note that every time the beta register is written with the tse bit = 1, a temperature compensation cycle is instigated and a new correction value will be loaded into the fatr/fdtr registers (if the temperature changed since the last conversion). also note that registers 0bh and 0ch, the itr0 and alpha registers, should not be changed. if they must be written be sure to write the same values that are recalled from initial power-up. the itr0 register may be written if the user wishes to re-calibrate the oscillator frequency at room temperature for aging or board mounting. the original recalled value can be re-written if desired after testing. for further information on the operation of the isl12022 and temperature compensated rtc? s, see intersil application note an1389, ?using intersil?s high accuracy real time clock module?. http://www.intersil. com/data/an/an1389.pdf daylight savings time (dst) example dst involves setting the forward and back times and allowing the rtc device to automatically advance the time or set the time back. this can be done for current year, and future years. many regions have dst rules that use standard months, weeks and time of the day which permit a pre-programmed, permanent setting. table 27 shows the exampl e setup for the isl12022. the enable bit (dste) is in the month forward register, so the bcd value for that register is altered with the additional bit. the week and day values along with week/day vs date select bit is in the week/day register, so that value is also not straight bcd. hour and m onth are normal bcd, but the hour doesn?t use the mil bit since military time pm values are already discretely different from am/pm time pm values. the dst reverse setting utilizes the option to select the last week of the month for october, which could have 4 or 5 weeks but needs to have the time change on the last sunday. note that the dstadj bit in the status register monitors whether the dst forward adjustment has happened. when it is ?1?, dst forward has taken place. when it is ?0?, then either dst reverse has happened, or it has been reset either by initial power-up or if the dste bit has been set to ?0?. ppm error f ( out 1 ) 1e6 ? ? = (eq. 8) table 27. dst example variable value register value month forward and dst enable april 15h 84h week and day forward and select day/week, not date 1st week and sunday 16h 48h date forward not used 17h 00h hour forward 2am 18h 02h month reverse october 19h 10h week and day reverse and select day/week, not date last week and sunday 1ah 78h date reverse not used 1bh 00h hour reverse 2am 1ch 02h isl12022
28 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6659.2 june 23, 2009 isl12022 small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 8 0 8 - rev. 1 6/05

▲Up To Search▲

Price & Availability of ISL12022IBZ

	To Download ISL12022IBZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .